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  1. #1
    PJ - BringJackBack user1's Avatar
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    Question Intel's DDR Dynamic Paging Mode - What is it?

    You all have probably already addressed this. If so, I could not find it by searching. And Bleeding Edge is OCX Memory right. Since I have some good ol OCZ 3700 Gold DC 2x256 Dual sided memory I figured I could get these questions answered intelligently here.....

    I have read Intel's Intel® 875P Chipset Memory Configuration Guide White Paper dated April 2003. In discussing the 875P Chipset as used my Asus p4c800e-deluxe, the article states:
    "The MCH supports the following modes of operation:
    1. Virtual Single-Channel (VSC) or Single-Channel Mode.
    2. Dual-Channel Lock Step mode (DS). (DS Linear Mode)

    The 875P chipset also supports a special mode of addressing – dynamic addressing mode. ALL the above-mentioned modes can be enabled with/without dynamic paging mode."

    I understand single channel, virtual single channel, dual channel linear mode; ...but what is dynamic addressing and/or paging mode??

    Intel states: " When the MCH is configured to operate in this mode, Front-Side Bus (FSB) to Memory Bus address mapping undergoes a significant change compared to that of in a linear operating mode (normal operating mode). In non-dynamic paging mode, the Rank selection (Rank or ROW
    indicates the side of a DIMM) via chip select signals, is done based on the size of the ROW. For example, for a 512-Mb 16MX8X4b will have a ROW size of 512 MB, selected by CS0#, and only four open pages can be maintained for the full 512 MB. This will lower the memory performance (increases READ latencies) if most of the memory cycles are targeted to that single ROW resulting in opening and closing of accessed pages in that ROW."

    Beyound this point is unknown territory for me. Is intel addressing DRAM configurations on a DIMM as having something to do with "Dynamic Paging Mode" If so, does that mean DIMMs that are not DRAM configured in a certain way are incapable of Dynamic/Paging Mode?

    When I boot my Asus P4c800e-d with 875P chipset and 2x256 PC 3700 OCZ double side DIMM modules, the bios screen says "Dual Channel, Linear Mode".

    How do confirm or configure that the system operates in Intel's "Dynamic Paging/Dynamic Addressing Mode" ?

    thank you.
    Last edited by user1; 05-10-2004 at 11:16 PM. Reason: correction

  2. #2

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    that is an easy question... Linear mode is defined in the Intel Specs as meaning two DIMMs in the same channel to be combined to 128 bit width.

    Dynamic addressing is a change in the paging sequence, that is the access of the internal banks that is mostly done in order to support integrated graphics on the 865G chipset in order to avoid bank conflicts where bank refers to the internal banks on the memory chips. This is also called GMCH-mode.


    Here's another explanation:

    Dynamic mode on the other hand refers to the addressing scheme of the internal Banks (not ranks) in that instead of doing a 0-1-2-3 (4 bank sequential interleaving) a 0-1-0-1 followed by 2-3-2-3 interleaving as defined by a certain block size is done.

    In other words, the fact that your BIOS says "Linear" mode is only a different word for Dual Channel. The "Dynamic Paging Mode" is completely transparent to the user, that is, it is handled internal on the memory controller and only refers to the sequence in which the internal banks on the memory chip are accessed.

    Dynamic mode is enabled in all cases by default as long as you have matching pairs or 4 identical DIMMs, only if you are pairing single and double-sided DIMMs with each other, it will fall back into "normal mode" which is the standard 4 bank interleaving without extended page boundaries through combining the page size on the two "linear" Ranks.

    I know that this is a bit complicated but here is an analogy:

    You have one book and by default you have two pages open (the one on the left and the other one on the right)

    If you have two identical books, you can open them at consecutive pages like page 2+3 and 4+5 and put them one above the other, in this case, your reading pattern will be 2-3-4-5 in a "Z" pattern.

    You can also rip the two books apart and combine pages 2 (from book #1) with page 3 (from book #2) by glueing page 3 to the bottom of page 2 and then do the same for pages 4 and 5.

    In that case, your "page size" increases and you don't have to switch that often. So you are going to be reading pages 2+3 and the 4+5. That's all there is to that

  3. #3
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    Unregistered, easy or not, that's the best explanation of that topic I've ever read

  4. #4
    PJ - BringJackBack user1's Avatar
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    Question Back Again with basic follow UP for Anonymous

    UNREGISTERED stated in his first post the following ("quotes" excerpted):

    "that is an easy question... Linear mode is defined in the Intel Specs as meaning two DIMMs in the same channel to be combined to 128 bit width."

    QUESTION: The i875P white paper indicates tha linear mode can also be two dimms; one in each channel (chapter 2.3 figure 6)

    "Dynamic addressing is a change in the paging sequence, that is the access of the internal banks that is mostly done in order to support integrated graphics on the 865G chipset in order to avoid bank conflicts where bank refers to the internal banks on the memory chips. This is also called GMCH-mode. "

    COMMENT: I follow that. I do note the referenced White paper is specifc to the 875P chipset however.

    "Here's another explanation:

    Dynamic mode on the other hand refers to the addressing scheme of the internal Banks (not ranks) in that instead of doing a 0-1-2-3 (4 bank sequential interleaving) a 0-1-0-1 followed by 2-3-2-3 interleaving as defined by a certain block size is done."

    COMMENT: Still with you. The "certain block size comment throws me" but perhaps for a moment we can place that aside.

    "In other words, the fact that your BIOS says "Linear" mode is only a different word for Dual Channel. The "Dynamic Paging Mode" is completely transparent to the user, that is, it is handled internal on the memory controller and only refers to the sequence in which the internal banks on the memory chip are accessed."

    COMMENT: With due respect, how can the first sentence above be correct? If Linear is other that dynamic paging mode, than according to the WP, single channel can be linear just as dual channel can be linear; so how is "Linear only a different word for Dual Channel" . (Transparency of operation of the MCH is understood also.)

    "Dynamic mode is enabled in all cases by default as long as you have matching pairs or 4 identical DIMMs, only if you are pairing single and double-sided DIMMs with each other, it will fall back into "normal mode" which is the standard 4 bank interleaving without extended page boundaries through combining the page size on the two "linear" Ranks."

    COMMENT: This is the meat of the question for me...! You state, "Dynamic mode is enabled (transparently by the MCH - insert mine) in all cases by default as long as you have matching pairs or 4 identical DIMMs.." (By 'matching pairs' I assume you mean 1 pair of identical dimms ?)

    QUESTION: Is it safe to assume that IF an "Illegal Configuration" or a "non supported memory technology" (WP, chapters 1.1 and 1.2) were employed, all bets are off ? That is, do non sanctioned configurations render dynamic paging mode disabled? With non sanctioned memory installed, is a non-dynamic paging mode (linear?) the best one could expect???.

    Thank you....
    user1
    pushing it uphill in Atlanta, GA
    Last edited by user1; 05-13-2004 at 03:24 PM.

  5. #5

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    Thank you, Sir!

    BTW, the new OCZ PC3700EB rock!

  6. #6

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    wow....

  7. #7
    OCZ Rep AndyT's Avatar
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    Who is that unregistered man? Awsome job!
    If you need quick help from an OCZ support rep you can find email links in their signatures. I assist here as time permits and it's fine to email me if you need my personal attention. I look forward to helping you. Email Me Here . Thanks!

  8. #8
    PJ - BringJackBack user1's Avatar
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    Default To Unregistered

    First, I am on a learning curve with XP as I find its internals more complex than W98se or 95 ever was. And memory, always way over my head.....

    Second, and most important, thank you for replying to my post. I am definatley going to have to 'soak' in this one for a while, because I want to understand, at least as a layman, what the basic concepts that are involved here. So, perhaps, you'll make yourself available here more often, as I probably would like to confirm my understanding of your reply, AND it is apparent that not just I, but many have profitted from your answer to my question.

    thanks again,
    cheers
    Last edited by user1; 05-10-2004 at 11:19 PM. Reason: correction

  9. #9

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    no problemo, just ask or if you don't see me here, you can always grab me on my hideout: www.lostcircuits.com

    I know that memory, being such a simple device is kind of hard to understand, it really comes down to basics and if necessary, I'll explain them to you down to the transistor and core logic level - or else memory is like a book, data are being written into it and then they are available for reading.

    All you need is find the right page and then the right line within the page. You can keep the page open until there is nothing left to read or if you are among the hasty ones, you do the Japanese speed reading trick (but most wont succeed) and in the end your knowledge base will be mixed up just like you can corrupt your HDD with too short page open times.

    The dual channel is the same as buying two copies of the same book and glueing the pages on top of each other (Intel) whereas with the Athlon64 FX the situation is much more complicated since they apparently use bit-level striping which means that the y write one bit over one memory controller to one DIMM and the next one to the second.. I don't have first hand information on that, though, so don't quote me until I have verified this.

    gotto run now but more to follow

  10. #10

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    Anything else you want to know? Like programmable CAS latency..

  11. #11

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    Dang, you're cool

  12. #12

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    Unregistered beat me to it

    Damn I should pay more attention to the forums , he answers all the good questions

  13. #13

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    OK, lets go step by step

    "In other words, the fact that your BIOS says "Linear" mode is only a different word for Dual Channel. The "Dynamic Paging Mode" is completely transparent to the user, that is, it is handled internal on the memory controller and only refers to the sequence in which the internal banks on the memory chip are accessed."

    COMMENT: With due respect, how can the first sentence above be correct? If Linear is other that dynamic paging mode, than according to the WP, single channel can be linear just as dual channel can be linear; so how is "Linear only a different word for Dual Channel" . (Transparency of operation of the MCH is understood also.)

    Reply: I believe it is a matter of semantics. Linear mode refers to the 128 bit combination of two 64 bit DIMMs, which makes them look like a single channel. If you populate both channels with two DIMMs you get dual channel linear.. I know this is kind of nonsense but the Intel WP has a tendency to use the same term for mutually exclusive facts.

    Bottom line for my own understanding (and I have discussed this with a bunch of Intel engineers) is that if you combine two DIMMs to a 128 bit wide configuration, you call that linear mode and that is generally referred to as dual channel. In reality, there is no dual channel at all because it is a double-width channel but that is still linear and you cannot get that with a single DIMM or else with two DIMMs of different format.

    "Dynamic mode is enabled in all cases by default as long as you have matching pairs or 4 identical DIMMs, only if you are pairing single and double-sided DIMMs with each other, it will fall back into "normal mode" which is the standard 4 bank interleaving without extended page boundaries through combining the page size on the two "linear" Ranks."

    COMMENT: This is the meat of the question for me...! You state, "Dynamic mode is enabled (transparently by the MCH - insert mine) in all cases by default as long as you have matching pairs or 4 identical DIMMs.." (By 'matching pairs' I assume you mean 1 pair of identical dimms ?)

    QUESTION: Is it safe to assume that IF an "Illegal Configuration" or a "non supported memory technology" (WP, chapters 1.1 and 1.2) were employed, all bets are off ? That is, do non sanctioned configurations render dynamic paging mode disabled? With non sanctioned memory installed, is a non-dynamic paging mode (linear?) the best one could expect???.


    Matching pairs would be two pairs of identical (within the pair) DIMMs. I still don't know what you mean with theh Illegal Configurations but I haven't had time to even look at that data sheet (been reading Intel datasheets for about 8 hours today and that was all I could take)

  14. #14

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    Only simple question: Intel chipset supports or not "bank interleave"!?

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