Athlon 64 to get Dual Channel DDR in 2004

[DivideBYZero]

Here (http://www.japseye.com/viewcontent.asp?articleid=246&preprod=1&Heading=Athlon%2064%20to%20go%20Dual%20Channel)

[compudog]

Very interesting indeed! Thanks /0 !!!

[JayisunJ]

I am usually pretty sceptical of any news article that starts out with "Sources indicate. . ." Very interesting none the less! :wave:

[DivideBYZero]

Originally posted by JayisunJ
I am usually pretty sceptical of any news article that starts out with "Sources indicate. . ." Very interesting none the less! :wave:

Source was PC Watch, and yes, maybe I'll change the way I write them.......:D

[JayisunJ]

Source was PC Watch, and yes, maybe I'll change the way I write them....... Hey man, your website (it is your website right?) is pretty cool. Reminds me of the inquirer. Your news section could be categorized by date or under the same heading for each different day, but otherwise it is pretty well layed out. :wave:

[Jeff7181]

I have to say, I think this is made up... the Athlon-64's memory controller will be part of the CPU... each CPU has 6.4 GB of memory bandwidth at it's fingertips because of that... and the Opterons with Hyper-Transport will have 6.4 GB PER CPU! So in an 8 way server, it would have 51.2 GB of total memory bandwidth. Not to mention it's other two Hyper-Transport "channels" that each CPU has.

[DivideBYZero]

Originally posted by Jeff7181
I have to say, I think this is made up... the Athlon-64's memory controller will be part of the CPU... each CPU has 6.4 GB of memory bandwidth at it's fingertips because of that... and the Opterons with Hyper-Transport will have 6.4 GB PER CPU! So in an 8 way server, it would have 51.2 GB of total memory bandwidth. Not to mention it's other two Hyper-Transport "channels" that each CPU has.

Firstly, this is A64, not Opteron, so only 1 bank of RAM. What this means is that there may well be an internal HT bus to the internal MEM controller(sum 1 who can be arsed to read the tech docs can tell me how the cpu 'talks' to the MC), but Controller to RAM will still be single channel DDR at launch.

Single channel DDR 333 of 400 will still only be a theoretical bandwidth of 2.7 or 3.2Gb, between the MC and the RAM itself. Dual channel would double it obviously and therefore DOES make sense.

[DivideBYZero]

Originally posted by JayisunJ
Hey man, your website (it is your website right?) is pretty cool. Reminds me of the inquirer. Your news section could be categorized by date or under the same heading for each different day, but otherwise it is pretty well layed out. :wave:

It is mine and thanks.

If I was to head up the articles under the day, then some days would look pretty bleak.... :D

[compudog]

I like the site /o. It loads quick too.

[DivideBYZero]

Originally posted by compudog
I like the site /o. It loads quick too.

It's a hosted server on a 10mb link. :D